In recent years, a new fine processing technology has been developed in accordance with high integration and high performance of large scale integration (LSI). A chemical mechanical polishing (CMP) method is one of those technologies, and it is often used in an LSI manufacturing process, particularly in planarizing an interlayer insulating film in a multilayer wiring forming process, forming a metal plug, and forming embedded wiring (damascene wiring).
The CMP has been applied to each step for manufacturing a semiconductor, and, as one example of the applications, an application to a gate forming step for manufacturing a transistor can be mentioned, for example. For manufacturing a transistor, there may be a case in which materials such as metal, silicon, silicon oxide, polycrystalline silicon (polysilicon), and silicon nitride are polished, and there is need for polishing each material at high speed to enhance the productivity.
In order to meet those needs, there is a technique in which an improvement is made for the abrasive grains to be contained in a polishing composition (Patent Literature 1). The abrasive grain to be contained in the polishing composition, which is disclosed in Patent Literature 1, is colloidal silica that is immobilized with an organic acid like sulfonic acid and carbonic acid. It is described that, as the abrasive grains are contained in the polishing composition, the object to be polished described in the same literature is polished at high speed.